A System On Chip Dedicated To Pipeline Neighborhood Processing For Mathematical Morphology

Also available at http://www.eurasip.org/Proceedings/Eusipco/Eusipco2008/papers/1569104317.pdfInternational audienceThis paper describes a system on chip for image processing. It is based on a pipe-line of neighborhood processors named SPoC and is controlled by a general purpose processor. Each SPoC are connected one to the other through a reconfigurable data path to get more adaptability and their structure exploits temporal and spatial parallelism to speed up computations and minimize memory transfers. Two applications, a motion detection algorithm and a licence plate extraction, are presented to show performances in terms of speed, embeddability and re-usability of the SoC. Comparisons with many architectures such as digital signal processors, workstations or embedded SIMD processors are made to benchmark the platform and prove the originality and the strength of our solution

Architectures flot de données dédiées au traitement d'images par morphologie mathématique

This thesis report is focused on studying data flow accelerators dedicated to image using mathematical morphology. The main objective is to provide a programmable and efficient implementation of basic morphological operators, and to assemble them in such a way as to provide complex operators with fast operation. In recent years, morphological algorithm research has been oriented towards finding elegant algorithms to compute these complex operators, such as watershed using priority queues. These complex algorithms often use specific data structures that are hard to deploy on platforms other than single-core, general-purpose processors. Moreover, these processors continue their development in the field of parallelism by heightening the number of cores. And because the frequency wall seems to have been reached, the best way to optimise performance is to use parallelising techniques. Consequently, we decided on fast implementations of complex mathematical morphology operators, based on highly parallel simpler operations. In the first part, we study existing computational kernels for neighbourhood processors and suggest new ones based on recent advances in mathematical morphology. In the second part, we use the neighbourhood processors as building blocks to generate and manage pipeline using high-level tools in a system on chip context. In the third part, we present a description of a basic VLIW processor using vector instructions deployed in a dataflow context to exploit spatial and temporal parallelism. Finally, we analyse the performance of our system against a multi-core workstation processor, and against a graphics processor to show the relevance of our approach.Nous abordons ici la thématique des opérateurs et processeurs flot de données dédiés au traitement d'images et orientés vers la morphologie mathématique. L'objectif principal est de proposer des architectures performantes capables de réaliser les opérations simples de ce corpus mathématique afin de proposer des opérateurs morphologiques avancés. Ces dernières années, des algorithmes astucieux ont été proposés avec comme objectif de réduire la quantité des calculs nécessaires à la réalisation de transformations telle que la ligne de partage des eaux. Toutefois, les mises en œuvre proposées font souvent appel à des structures de données complexes qui sont difficiles à employer sur des machines différentes des processeurs généralistes monocœurs. Les processeurs standard poursuivant aujourd'hui leur évolution vers une augmentation du parallélisme, ces implémentations ne nous permettent pas d'obtenir les gains de performance escomptés à chaque nouvelle génération de machine. Nous proposons alors des mises en œuvre rapides des opérations complexes de la morphologie mathématique par des machines exploitant fortement le parallélisme intrinsèque des opérations basiques. Nous étudions dans une première partie les processeurs de voisinage travaillant directement sur un flot de pixels et nous proposons différentes méthodologies de conception rapide de pipelines dédiés à une application. Nous proposons également une structure de pipeline programmable via l'utilisation de processeurs vectoriels avec différentes possibilités de chaînage. Enfin, une étude avec des machines est proposée afin d'observer la pertinence de notre approche

Definition Of A Regular, Configurable Simd Architecture For Image Processing Accelerators

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New solutions and technologies for uncooled infrared imaging

International audienceThe military uncooled infrared market is driven by the continued cost reduction of the focal plane arrays whilst maintaining high standards of sensitivity and steering towards smaller pixel sizes. As a consequence, new optical solutions are called for. Two approaches can come into play: the bottom up option consists in allocating improvements to each contributor and the top down process rather relies on an overall optimization of the complete image channel. The University of Rennes I with Thales Angénieux alongside has been working over the past decade through French MOD funding's, on low cost alternatives of infrared materials based upon chalcogenide glasses. A special care has been laid on the enhancement of their mechanical properties and their ability to be moulded according to complex shapes. New manufacturing means developments capable of better yields for the raw materials will be addressed, too. Beyond the mere lenses budget cuts, a wave front coding process can ease a global optimization. This technic gives a way of relaxing optical constraints or upgrading thermal device performances through an increase of the focus depths and desensitization against temperature drifts: it combines image processing and the use of smart optical components. Thales achievements in such topics will be enlightened and the trade-off between image quality correction levels and low consumption/ real time processing, as might be required in hand-free night vision devices, will be emphasized. It is worth mentioning that both approaches are deeply leaning on each other. © (2013) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only

FREIA ANT-AF-2007-004

National audiencePrésentation détaillée du projet FREIA ANR-AF-2007-00

A Design Flow for Critical Embedded Systems

International audienceThe SoCKET project (SoC1 toolKit for critical Embedded sysTems)2 gathers industrial and academic partners to address the issue of design methodologies for critical embedded systems. They work towards the definition of a “seamless” design flow which integrates qualification and certification, from the system level to integrated circuits and to software. This paper sketches such a design flow and the associated methodologies, and briefly describes its application to industrial case studies

Design of Fixed-Point Embedded Systems (defis) French ANR Project

International audienceEmbedded applications are usually coming with stringent constraints in term of cost, energy consumption and real-time. Consequently, fixed-point arithmetic is mainstream for their implementation into embedded systems. Hence, the main objective of the french ANR project DEFIS is to provide a complete design flow for fixed-point refinement of complex applications. This tool flow is like the missing link between high-level application specification tools and low-level implementation